A Hardware and Secure Pseudorandom Generator for Constrained Devices

Hardware security for an Internet of Things or cyber physical system drives the need for ubiquitous cryptography to different sensing infrastructures in these fields. In particular, generating strong cryptographic keys on such resource-constrained device depends on a lightweight and cryptographically secure random number generator. In this research work, we have introduced a new hardware chaos-based pseudorandom number generator, which is mainly based on the deletion of an Hamilton cycle within the N-cube (or on the vectorial negation), plus one single permutation. We have rigorously proven the chaotic behavior and cryptographically secure property of the whole proposal: the mid-term effects of a slight modification of the seed (proven to be sensitive to the initial conditions) or of the inputted generator cannot be predicted. The proposal has been fully deployed on a FPGA and 65 nm ASIC, it runs completely in parallel while consuming as low resources as possible, and achieving: (a) 11.5 Gb/s for FPGA and 9.4 Gb/s for ASIC random bit throughput, (b) 3.3 mu W (LF) to 7.8 mW (UHF) total power consumption with 5% leakage power, measured at 1.32 V, and (c) able to successfully pass the statistical tests of NIST and TestU01 (BigCrush).