CIPRNG: A VLSI Family of Chaotic Iterations Post-Processings for F-2-Linear Pseudorandom Number Generation Based on Zynq MPSoC

Hardware pseudorandom number generators are continuously improved to satisfy both physical and ubiquitous computing security system challenges. The main contribution of this paper is to propose two post-processing modules in hardware, to improve the randomness of linear PRNGs while succeeding in passing the TestU01 statistical battery of tests. They are based on chaotic iterations and are denoted by CIPRNG-MC and CIPRNG-XOR. They have various interesting properties, encompassing the ability to improve the statistical profile of the generators on which they iterate. Such post-processing have been implemented on FPGA and ASIC without inferring any blocs (RAM or DSP). A comparison in terms of area, throughput, and statistical tests, is performed. The hardware pseudorandom number generation can reach a throughput/latency ratio equal to 8.5 Gbps for Zynq-FPGA and 10.9 Gbps for ASIC, being thus the fastest FPGA generators based on chaos that can pass TestU01. In particular, it is established that CIPRNG-XOR is 2.5 times faster and 5 times more efficient that almost all linear PRNGs who pass TestU01.