MARTE and IP-XACT based approach for run-time scalable NoC

The Networks on chip (NoC) based communication is increasingly used as a solution for multiIP system-on-Chip. There have been tremendous works to improve the adaptation of the NoC for FPGA based dynamically reconfigurable IPs. The Dynamic Partial Reconfiguration (DPR) based run-time scalable NoC is one way to reduce the power consumption by idle components of the NoC. However, the absence of custom HDL NoC generation tools which separate the NoC rows and columns into independent components remains open. In this paper, we have introduced a UML/MARTE and IPXACT based approach to model and generated runtime scalable NoC components targeting Xilinx FPGAs. The NoC is modeled by splitting into static sub-NoC and a series of run-time scalable rows and columns as a component. First, both the static and run-time scalable sub-NoC are defined at a high level using the UML/MARTE. Then, they are transformed into an intermediate level of XML description respecting the IP-XACT standard. Next, all XML description of the top level NoC, the reconfigurable rows and columns are transformed into VHDL. Finally, the HDL files of the NoC are imported to Xilinx EDK to implement the dynamically scalable NoC by mixing with the FPGA based reconfigurable IPs. The proposed approach is validated by modeling a 3x3 NoC splitting into three components as 2x2 static sub-NoC, 2x1 reconfigurable column and 1x3 reconfigurable row. Then, a user-defined small IPs are used to connect with the NoC routers and implement the full system.