Revisiting the High-Performance Reconfigurable Computing for Future Datacenters

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TitreRevisiting the High-Performance Reconfigurable Computing for Future Datacenters
Type de publicationJournal Article
Year of Publication2020
AuteursIjaz Q, Bourennane E-B, Bashir AKashif, Asghar H
JournalFUTURE INTERNET
Volume12
Pagination64
Date PublishedAPR
Type of ArticleReview
Mots-clésdatacenters, FPGA virtualization, multi FPGA, multi tenancy, Network on Chip, reconfigurable computing
Résumé

Modern datacenters are reinforcing the computational power and energy efficiency by assimilating field programmable gate arrays (FPGAs). The sustainability of this large-scale integration depends on enabling multi-tenant FPGAs. This requisite amplifies the importance of communication architecture and virtualization method with the required features in order to meet the high-end objective. Consequently, in the last decade, academia and industry proposed several virtualization techniques and hardware architectures for addressing resource management, scheduling, adoptability, segregation, scalability, performance-overhead, availability, programmability, time-to-market, security, and mainly, multitenancy. This paper provides an extensive survey covering three important aspects-discussion on non-standard terms used in existing literature, network-on-chip evaluation choices as a mean to explore the communication architecture, and virtualization methods under latest classification. The purpose is to emphasize the importance of choosing appropriate communication architecture, virtualization technique and standard language to evolve the multi-tenant FPGAs in datacenters. None of the previous surveys encapsulated these aspects in one writing. Open problems are indicated for scientific community as well.

DOI10.3390/fi12040064