An efficient hardware solution for 3D-HEVC intra-prediction

Three-dimensional high-efficiency video coding (3D-HEVC) is the highest profile extension of HEVC for 3D video coding that supports the advanced 3D video format, multi-view video plus depth (MVD). Depth modelling modes (DMMs) are adopted into 3D-HEVC to preserve sharp edges and avoid ringing artefacts in synthesized views. However, computational complexity increases significantly with these modes. A novel hardware solution that reduces the complexity of DMMs for 3D-HEVC is presented in the present paper. This solution contains five modules working in parallel to find all DMMs defined in the new standard for all depth block sizes (from 4 x 4 to 32 x 32). A new technique for obtaining the most compatible wedgelet pattern with its own syntax is developed to minimize the quantity of calculations coming from DMM1; the aforementioned information (wedgelet pattern and syntax) is already calculated and stored in an external memory. This design is synthesized for a Xilinx Virtex 6 FPGA and can process up to 30 frames per second (FPS) while considering the encoding of 6 full HD views in real time. The proposed solution can reach a processing rate up to 30 FPS for 4 QHD views in real time when using 4K video encoding.