A templated programmable architecture for highly constrained embedded HD video processing

The implementation of a video reconstruction pipeline is required to improve the quality of images delivered by highly constrained devices. These algorithms require high computing capacitiesseveral dozens of GOPs for real-time HD 1080p video streams. Today's embedded design constraints impose limitations both in terms of silicon budget and power consumptionusually 2mm2 for half a Watt. This paper presents the eISP architecture that is able to reach 188MOPs/mW with 94GOPs/mm2 and 378GOPs/mW using TSMC65-nm integration technology. This fully programmable and modular architecture, is based on an analysis of video-processing algorithms. Synthesizable VHDL is generated taking into account different parameters, which simplify the architecture sizing and characterization.