FPGA based hardware in the Loop Test of Railway Traction System
| Affiliation auteurs | !!!! Error affiliation !!!! |
| Titre | FPGA based hardware in the Loop Test of Railway Traction System |
| Type de publication | Conference Paper |
| Year of Publication | 2018 |
| Auteurs | Liu C, Ma R, Hao B, Luo H, Gao F, Gechter F |
| Conference Name | 2018 IEEE INTERNATIONAL CONFERENCE ON INDUSTRIAL ELECTRONICS FOR SUSTAINABLE ENERGY SYSTEMS (IESES) |
| Publisher | Inst Elect & Elect Engineers; Univ Waikato; IEEE Ind Elect Soc |
| Conference Location | 345 E 47TH ST, NEW YORK, NY 10017 USA |
| ISBN Number | 978-1-5090-4974-5 |
| Mots-clés | dSpace, FPGA, Hardware In The Loop, High speed train, traction system |
| Résumé | Hardware in the loop (HIL) test provides a time-saving and safe environment for testing prototypes. However, the main difficulty for the real time simulation of power electronic system is the modeling method for the complex system. This paper proposes a modeling method fir traction system in high speed train for transportation application. In this paper, it proposes hardware in the loop test setup for railway high-speed train with field-programmable gate array (FPGA) boards of dSPACE simulator. Besides, in order to meet the computing power requirement of the system modeling, a multi-processor system of dSPACE is achieved through Gigalink connection. The whole HIL system can he used to evaluate both the hardware and software performance of traction control unit (TCU). The real time simulation results under steady-state and transient conditions demonstrate modeling accuracy and provide detailed insight into the development of this vehicle. |