Very High Level Synthesis for image processing applications

Since the recent 20 years, High Level Synthesis (HLS) has made significantly progresses. This technique greatly benefits the R&D productivity of the FPGA designs and helps for adding to the maintainability of the products by automating the C-to-RTL conversion. However, due to the high complexity and computational intensity, image processing designs usually necessitate a higher abstraction level than C-synthesis, and the current HLS tools do not have the ability of this kind. This paper presents a Very High Level Synthesis method which allows fast prototyping and verifying the FPGA designs in the Matlab environment. We build a heterogeneous design flow by using currently-available tool kits for verifying the proposed approach and evaluated it within two real-life applications. Experiment results demonstrate that it can effectively reduce the complexity of the design and give play to the advantages of FPGAs related to the other devices.