A Novel Hardware Accelerator for the HEVC Intra Prediction
| Affiliation auteurs | !!!! Error affiliation !!!! |
| Titre | A Novel Hardware Accelerator for the HEVC Intra Prediction |
| Type de publication | Conference Paper |
| Year of Publication | 2015 |
| Auteurs | Amish F, Bourennane E-B |
| Conference Name | 2015 IEEE 13TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) |
| Publisher | IEEE |
| Conference Location | 345 E 47TH ST, NEW YORK, NY 10017 USA |
| ISBN Number | 978-1-4799-8893-8 |
| Mots-clés | FPGAs, HEVC, Intra prediction |
| Résumé | A novel hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity within this standard and to accelerate the concerned calculations. We propose a new pipelined structure that we called Processing Element (PE) to execute all angular modes, and we repeat it in five paths that our architecture composed of. We present also another structure to carry out the Planar mode. This architecture supports all intra prediction modes for all prediction unit sizes. The synthesis results show that our design can run at 213 MHz for Xilinx Virtex 6 and is capable to process real time 120 1080p FPS or 30 4K FPS. To the best of our knowledge, it outperforms all hardware solutions existing in the literature. |