Connection of H.264/AVC hardware IPs using a specific Networks-on-Chip

Real time and high quality video coding assured by new codec's as the H.264/AVC is gaining a wide interest in the research and industrial community for different applications. Several new hardware implementations (IPs) have been proposed for the various processing elements of video codec's. At the same time, several works have been proposed to integrate this IPs in single System-on-Chip (SoC) aiming to provide multi-processor systems (MPSoC) based on shared-bus architecture. Generally these systems present the disadvantages of signal propagation delays and signal integrity and scalability depending on the number of cores used. Network-on-Chip is a newly introduced paradigm to overcome the communication problems of System-on-Chip architectures. In this paper we propose an optimized hardware architecture for the H.264/AVC using a Network-on-Chip. Firstly, we performed a 3 x 3 mesh Network-on-Chip and then we connect the hardware IPs proposed for the H.264/AVC using a specific Network-Interface. We use only the information available on the H.264/AVC to locate manually the position of IPs on the network. The synthesis results of our implementations are compared with the ordinary shared-bus based network. Finally, we embed the Network-on-Chip based system in a complete System-on-Chip using the MicroBlaze processor and we compare the results. (C) 2015 Elsevier B.V. All rights reserved.