Utilisation of the Array-OL specification language for self-generation of a memory controller especially for the H.264/AVC

H.264/AVC has been introduced in recent years to decrease the bit-rate and to increase the flexibility of implementations. After careful study and analysis, we have concluded that the complexity of this video codec depends mainly on its multidimensional data dependency, its elementary processing modules and its various profiles and levels. In this paper, we have proposed several Array-OL models especially for the modelling of data flow between the processing modules for self-generation of vhdl code of a memory controller for H.264/AVC. The controller will be adapted to the application profiles and levels and the used external memory. The proposed models combined with high level modelling tools should be used to perform embedded systems; the goal is the automatic generation of the Netlist from a high level description. The methodology is demonstrated by an example in which a specific level of the H.264/AVC is generated from information given by the proposed Array-OL models. The generated vhdl code is synthesised using two FPGA development board with ratios of used LUTs that do not exceed 10% and verified to work at 263 MHz frequency.