Power-Efficient Partially-Adaptive Routing in On-chip Mesh Networks
| Affiliation auteurs | !!!! Error affiliation !!!! |
| Titre | Power-Efficient Partially-Adaptive Routing in On-chip Mesh Networks |
| Type de publication | Conference Paper |
| Year of Publication | 2016 |
| Auteurs | Jalili M., Bourgeois J., Sarbazi-Azad H. |
| Conference Name | 2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) |
| Publisher | IEEE; Inst Elect & Informat Engineers; IEEE Circuits & Syst Soc; IC Design Educ Ctr; KETI; KSIA; ETRI; Korea Tourism Org; Jeju Convent & Visitors Bur |
| Conference Location | 345 E 47TH ST, NEW YORK, NY 10017 USA |
| ISBN Number | 978-1-5090-3219-8 |
| Mots-clés | Mesh, Network-on-chip (NoC), performance, Power consumption, Routing algorithm, simulation |
| Résumé | The mesh network-on-chip (MNoC) is the most popular inter-processor communication infrastructures used in modern on-chip systems. Although many routing algorithms have been developed for MNoCs but almost all of them give better performance in cost of more complexity (more virtual channels) and hence extra power consumption. In this paper, we propose a partially adaptive routing algorithm for meshes that requires no virtual channels to ensure deadlock freedom. Simulation experiments show that the proposed method provides good performance while using less power consumption. |